1. Field
Exemplary embodiments of the present invention relate to semiconductor design technology, and more particularly, to a multi-chip package including a plurality of semiconductor devices.
2. Description of the Related Art
In general, semiconductor devices such as double data rate synchronous DRAM (DDR SDRAM) have developed in various ways (e.g., a package technology) to satisfy users' needs. Recently, a multi-chip package has been suggested as the package technology for semiconductor devices. The multi-chip package refers to a single apparatus including a plurality of semiconductor devices (i.e., chips or dies). The multi-chip package may increase a memory capacity using a plurality of memory devices with a memory function and secure desired performance using semiconductor devices with different functions. For reference, the multi-chip package may be a single-layer multi-chip package or a multilayer multi-chip package. The single-layer multi-chip package includes a plurality of semiconductor devices arranged in parallel on the plane, and the multilayer multi-chip package may include a plurality of semiconductor devices stacked therein.
Conventionally, when a plurality of semiconductor chips are implemented as a multilayer multi-chip package, input/output terminals of semiconductor devices are wire-bonded. However, when wire bonding is used, the multi-chip package may not satisfy a high-speed operation and may be vulnerable to various noises. Thus, through-silicon via (TSV) technology has been recently used in place of the wire bonding.
The multi-chip package may be implemented as a double-die package (DDP), quad-die package (QDP), or octo-die package (ODP). A DDP represents operation of two semiconductor devices, QDP represents operation of four semiconductor devices, and ODP represents operation of eight semiconductor. In each of DDP, QDP, and ODP, before a normal operation is performed, an address must be designated for each of the semiconductor devices in the multi-chip package.
FIG. 1 is a block diagram illustrating a conventional multi-chip package. A multi-chip package in which DDP and QDP operations are available will be taken as an example.
Referring to FIG. 1, the multi-chip package includes first to fourth semiconductor devices 110 to 140 and a controller 150.
The first to fourth semiconductor devices 110 to 140 may be activated in response to an address signal ADD generated by the controller 150. Among the first to fourth semiconductor devices 110 to 140, an activated semiconductor device performs a normal operation corresponding to a command signal (not illustrated). Thus, an order for addressing the semiconductor devices 110 to 140 is to be set. Conventionally, to set the order for addressing, option pads are used. The respective semiconductor devices 110 to 140 include option pad units P1 to P4. Then, according to settings of the option pad units P1 to P4, the order for addressing the first to fourth semiconductor devices 110 to 140, the controller 150 may activate a semiconductor device corresponding to the address signal ADD, and perform a normal operation.
As illustrated in FIG. 1, at least two option pads are required for the respective semiconductor devices 110 to 140. For example, in the configuration for ODP operation, at least three option pads are required for each semiconductor device. Recently, with the developments in process technology and design technology of semiconductor devices, the number of stacked semiconductor devices has gradually increased. As the number of the stacked semiconductor devices increases, the number of option pads also increases. The increase in the number of option pads may serve as a factor which increases the size and cost of the multi-chip package.